PTP — Precision Time Protocol (IEEE 1588)
Precision Time Protocol — IEEE 1588
For PTP in Dante networks, see networking/dante. For AES67 PTP configuration, see networking/aes67. For gPTP (IEEE 802.1AS, used in AVB), see networking/avb.
PTP (Precision Time Protocol), defined in IEEE 1588, synchronizes clocks across an IP network to sub-microsecond accuracy. In AV systems, Dante, AES67, AV-over-IP (Crestron NVX), and SMPTE ST 2110 all rely on PTP to ensure every device in the network shares the same absolute time reference. Without PTP, digital audio devices on a network drift apart in sample time, producing pops, clicks, dropouts, and eventually complete silence as buffers over- or under-run.
How PTP Works
PTP uses a master-slave hierarchy:
- Best Master Clock Algorithm (BMCA): devices on the network announce their clock characteristics (accuracy, stability, priority). The BMCA algorithm automatically elects the best clock as the grandmaster.
- Sync messages: the grandmaster sends periodic Sync messages timestamped with the exact transmission time.
- Delay Request/Response: each slave sends a Delay_Req message; the master responds with the receipt timestamp, allowing the slave to calculate round-trip path delay.
- Clock correction: the slave adjusts its local clock to account for offset and path delay, locking to the grandmaster's time.
IEEE 1588v2 achieves < 1 µs synchronization accuracy on a well-configured network. Hardware timestamping (in the network switch's silicon) is required for best accuracy — software timestamping adds jitter from OS scheduling.
PTP in Dante
Dante uses a proprietary PTP implementation but follows IEEE 1588v2 principles. The Dante Controller "Clock Status" view shows the current grandmaster and each device's offset (should be < 1 µs from grandmaster). A laptop running Dante Virtual Soundcard (DVS) should never be the Dante clock master — CPU load causes clock jitter. Designate a stable hardware Dante device as "Preferred Master" in Dante Device Manager.
Dante supports PTP v1 (1588v1) on older devices and PTP v2 (1588v2) on current devices. Ensure all devices in the system use the same PTP version — mixing v1 and v2 devices can cause clock instability. See networking/dante.
PTP in AES67 and SMPTE ST 2110
AES67 mandates IEEE 1588v2 PTP with hardware timestamping. The PTP domain number must be the same for all devices (default: domain 0 for most AV devices; domain 127 for Ravenna by default). SMPTE ST 2110 broadcast environments require:
- < 1 µs clock offset across all devices
- PTP grandmaster connected to a GPS or IEEE IRIG time source for absolute time reference
- Boundary clocks in network switches to prevent PTP traffic from overloading large networks
Boundary Clock vs. Transparent Clock vs. Ordinary Clock
| Type | Function | AV Use |
|---|---|---|
| Ordinary Clock | Simple slave or master; does not forward PTP | End devices (Dante gear, NVX, cameras) |
| Boundary Clock | Terminates PTP on one port; acts as master on other ports; prevents PTP flooding | Managed switches in Dante/AES67 networks |
| Transparent Clock | Measures residence time and corrects timestamps; forwards PTP end-to-end | Alternative to boundary clock in flat networks |
For large Dante or AES67 networks, configure switches with boundary clock support to prevent PTP Sync storm across many devices. Most enterprise-grade switches (Cisco Catalyst, Aruba CX) support boundary and transparent clock modes.
gPTP (IEEE 802.1AS)
gPTP is a profile of PTP optimized for AVB/TSN networks. It only runs over supported network paths (not across routers) and is faster-converging than standard PTP. gPTP is used by AVB audio devices and some video conferencing equipment. Dante and AES67 use standard IEEE 1588 PTP, not gPTP. See networking/avb.
Common Pitfalls
-
Laptop or PC as Dante clock master. Windows/macOS CPU scheduling jitter causes the PTP clock to wander, producing audio glitches across the entire Dante network. Fix: in Dante Device Manager, set a hardware Dante device as Preferred Master; verify DVS is not elected grandmaster in Clock Status view.
-
PTP domain mismatch. AES67 devices default to PTP domain 0; Ravenna devices default to domain 127. Devices on different domains cannot synchronize. Fix: configure all devices to the same domain number before deploying AES67 interoperability.
-
Software timestamping causing excessive PTP offset. A device relying on OS software for PTP timestamping shows offsets of 10–100 µs instead of < 1 µs. Fix: verify hardware timestamping is enabled on the NIC and switch port; use a NIC and switch that support IEEE 1588 hardware timestamps.
-
Not verifying PTP lock after network changes. Adding a new VLAN, switch, or device to the network can disrupt PTP topology. Fix: always check Dante Controller → Clock Status (or equivalent) after any network change to verify all devices are locked to the grandmaster with low offset.